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/* SPDX-License-Identifier: GPL-2.0 * * Copyright (C) 2018 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ #include <dt-bindings/clock/renesas-cpg-mssr.h> /* r8a77470 CPG Core Clocks */ #define R8A77470_CLK_Z2 0 #define R8A77470_CLK_ZTR 1 #define R8A77470_CLK_ZTRD2 2 #define R8A77470_CLK_ZT 3 #define R8A77470_CLK_ZX 4 #define R8A77470_CLK_ZS 5 #define R8A77470_CLK_HP 6 #define R8A77470_CLK_B 7 #define R8A77470_CLK_LB 8 #define R8A77470_CLK_P 9 #define R8A77470_CLK_CL 10 #define R8A77470_CLK_CP 11 #define R8A77470_CLK_M2 12 #define R8A77470_CLK_ZB3 13 #define R8A77470_CLK_SDH 14 #define R8A77470_CLK_SD0 15 #define R8A77470_CLK_SD1 16 #define R8A77470_CLK_SD2 17 #define R8A77470_CLK_MP 18 #define R8A77470_CLK_QSPI 19 #define R8A77470_CLK_CPEX 20 #define R8A77470_CLK_RCAN 21 #define R8A77470_CLK_R 22 #define R8A77470_CLK_OSC 23 #endif /* __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ */